The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs).
A FinFET is a non-planar device structure for a field-effect transistor that is capable of being more densely packed in an integrated circuit than planar field-effect transistors. A FinFET includes one or more fins of semiconductor material and an overlapping gate electrode that intersects a channel within the body of each fin. The channel in each fin is located between heavily-doped source/drain regions formed in fin sections that are not covered by the gate electrode. The fin dimensions and the number of fins determine the effective channel width of the FinFET.
Lithographic processes may be used to form the fins for a FinFET. For example, using optical photolithography, features can be formed by patterning a photoresist layer and an image of the features can be transferred into an underlying semiconductor layer to form fins. However, lithographic processes are incapable of satisfying the ever-increasing demand for smaller and more closely spaced fins.
Sidewall image transfer (SIT) involves the use of mandrels as sacrificial structures. Sidewall spacers, which have a thickness less than that permitted by the current ground rules for optical lithography, are formed on the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask and semiconductor layer, for example, with a directional reactive ion etching (RIE). Because the sidewall spacers may have a sublithographic line width, the fins formed from the underlying semiconductor layer will also have a sublithographic line width. The sidewall spacers are removed after the fins are formed.
A problem associated with forming semiconductor fins at tight pitch relates to the cutting of unwanted fins. As the available space between fins decreases, it becomes increasingly difficult to remove unwanted fins with etching and the assistance of a cut mask without adversely affecting adjacent fins due to process variation and small process margin of lithographic processes. Misalignment of the cut mask may lead to undesired partial or complete cutting of adjacent fins.
Improved methods for a lithographic process used to pattern fins for FinFETs are needed.